| Title | Priority Date | Status | Referenced by other patents | Overview of claims |
| FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions | July 29, 1992 | Issued November 4, 1997 |
190 | Runtime generation of bitstreams. |
| Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed | July 29, 1992 | Issued September 1, 1998 |
229 | Continuation of 5,684,980 Runtime configuration over a network. Computing with FPGAs interconnected over a network. |
| Computer with programmable arrays which are reconfigurable in response to instructions to be executed | July 29, 1992 | Issued February 8, 2000 |
128 | Continuation in part of 5,684,980 Partial runtime reconfiguration (PRTR) This patent's claims used the term Field Programmable Gates, FPGs. |
| Modular, hybrid processor and method for producing a modular, hybrid processor | September 23, 1996 | Issued January 23, 2001 |
69 | Intel 80486 and Xc6200 in the same package (and then on the same die) , pin compatible with the 80486. Says both could be on the same die. Basically the first FPGA plus processor chip. |
| Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs |
July 29, 1992 | Issued September 11, 2001 |
98 | Continuation in part of 5,684,980 More PRTR claims. Compiling FPGAs on FPGAs. |
| FPGA co-processor for accelerated computation | Jul 28, 2006 | Issued December 21, 2010 |
13 | FPGA in the CPU (AMD Opteron) socket. Otherwise known as "the socket stealing" patent |
| Configurable processor module accelerator using a programmable logic device | Jul 28, 2006 | Issued December 21, 2010 |
14 | FPGA in CPU socket with extra memory. |
| Reconfiguration of an accelerator module having a programmable logic device | Feb 25, 2008 | Issued March 27, 2012 |
1 | Fully reconfiguring the FPGA in the CPU socket during runtime without rebooting. |
| Accelerator system for use with secure data storage | May 28, 2010 | Issued December 3, 2013 |
0 | A way to encrypt and handle data in a way that the OS thinks it touched the data but the data all goes through the FPGA. |
| Accelerator system for remote data storage | May 27, 2011 | Issued September 2, 2014 |
0 | Basically Software Defined Networking (SDN) and Network Function Virtualization (NFV) for FPGAs |
| Memory architecture optimized for random access | June 1, 2012 | Issued March 10, 2015 |
0 | A way to organize physical memory based on burst length for lower power and higher random access. |
| Placement based arithmetic operator selection | May 15, 2014 | Issued May 26, 2015 |
0 | A way to more efficiently use logic and DSP resources by doing a high level placement and congestion study then picking a DSP or logic implementation of your math. |